Semiconductor memory is widely used in various electronic devices such as mobile phones, digital cameras, personal digital assistants, SSDs, medical electronics, mobile computing devices, and non-mobile computing devices. Semiconductor memory may comprise non-volatile memory or volatile memory. A non-volatile memory allows information to be stored and retained even when the non-volatile memory is not connected to a source of power (e.g., a battery). Examples of non-volatile memory include flash memory (e.g., NAND-type and NOR-type flash memory) and Electrically Erasable Programmable Read-Only Memory (EEPROM).
It is common for semiconductor memory die to be placed into a package to allow for easier handling and assembly, and to protect the die from damage. Although a plural form of “die” is “dice,” it is common industry practice to use “die” as a plural form as well as the singular form. In one example, semiconductor memory die and/or other integrated circuits, such as processors, may be encased within a package wherein the die may be stacked on top of one another within the package. The package may comprise a surface-mount package (e.g., a BGA package or TSOP package). One benefit of vertically stacking die within a package (e.g., stacking 16 die within a single package) is that form factor and/or package size may be reduced. In some cases, the package may comprise a stacked multi-chip package, a system-in-package (SiP), or a chip stack multichip module (MCM). Vertical connections between the stacked die including direct vertical connections through a die's substrate (e.g., through a silicon substrate) may be formed within each die before or after die-to-die bonding. In some cases, the vertical connections may comprise through-silicon vias (TSVs).
FIGS. 1-3 depict various embodiments of a semiconductor package 20 including a plurality of stacked die. As depicted, a plurality of semiconductor die, such as die 22, 24, and 34 may be mounted to a substrate 26 and encased within the semiconductor package 20. In one example, each of die 22, 24, and 34 may comprise a semiconductor memory die. In another example, die 22 may comprise a flash memory die and die 24 may comprise a memory controller. In some embodiments, the number of vertically stacked die within a package may comprise more than two die (e.g., 16, 32, or 64 die within the package). Each of the semiconductor die may include bond pads on an upper surface of the die for allowing electrical access to integrated circuitry within the die. Each bond pad may correspond with an input pin, an output pin, or an input/output (I/O) pin that connects to the integrated circuitry. Wire bonding connections, such as bond wires 30, may be used to electrically connect a die with other die within the package or to substrate 26. The bond wires 30 may comprise a metal such as copper, aluminum, or gold.
As depicted in FIG. 1, two or more semiconductor die may be stacked directly on top of each other, thereby taking up a small footprint on the substrate 26. However, in a vertically stacked configuration without TSVs, space must be provided between adjacent semiconductor die for the bond wire connections. A dielectric spacer layer 33 may be used to provide space for the bond wires 30 to be bonded to bond pads on the lower die 24. As depicted in FIGS. 2-3, instead of stacking die directly above each other, each of the stacked semiconductor die may be offset such that the bond pads on one side of each die are exposed.